Phase Locked Loops

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

High Frequency / Silicon on Insulator / Bit Error Rate / Jitter / High performance / Phase Locked Loops / Phase Lock Loop / Integrated Circuit Design / Integrated Circuit Packaging / Transceivers / Phase Locked Loops / Phase Lock Loop / Integrated Circuit Design / Integrated Circuit Packaging / Transceivers

A method for linking process-level variability to system performances

Informatics / Statistical Analysis / Response Surface Methodology / VLSI / Very Large Scale Integration / Process Variation / System performance / Phase Locked Loops / Phase Lock Loop / Process Variation / System performance / Phase Locked Loops / Phase Lock Loop

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

High Frequency / Silicon on Insulator / Bit Error Rate / Jitter / High performance / Phase Locked Loops / Phase Lock Loop / Integrated Circuit Design / Integrated Circuit Packaging / Transceivers / Phase Locked Loops / Phase Lock Loop / Integrated Circuit Design / Integrated Circuit Packaging / Transceivers

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O

Digital Communication / Protocols / Silicon on Insulator / Jitter / High Speed / Solid State Devices and Circuits / Phase Locked Loops / Solid State Devices and Circuits / Phase Locked Loops

A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications

Phase Locked Loop / Low Power Electronics / Jitter / Electrical And Electronic Engineering / Phase Locked Loops / Charge Pumps

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